PDM Receiver/PDM-to-PCM Converter

This PDM2PCM is a configurable audio interface core that converts a mono or stereo Pulse Density Modulation (PDM) stream into standard Pulse Code Modulation (PCM) format. PCM output widths are programmable from 2 to 32 bits, and all standard audio sampling rates are achievable via an adjustable Oversampling Ratio (OSR) from 32x to 256x.

The processing pipeline enables high-fidelity PCM audio output. It consists of:

• a pin controller that samples PDM data on configurable clock edges,
• a CIC decimation filter that down samples to the target rate,
• a first-order IIR high-pass filter for DC/low-frequency noise removal (coefficient set in Q1.31 format),
• a digital programmable gain amplifier (PGA) which provides volume control from -114.4 dB to -30.1 dB, and
• a quantizer with dithering to minimize quantization noise.

Output saturation logic prevents PCM overflow, and a max amplitude register enables runtime clipping detection.

Designed for ease of integration, the core’s control and status registers (CSR) interface is selectable between AMBA® AXI-Lite and APB. Furthermore, the PCM data can be output either via an AXI4-Stream interface for continuous sample streaming, or AXI4 manager for burst writing large audio blocks directly to external memory.

The output FIFO/buffer size is synthesis-time configurable, while the address, transfer length, and burst length for the AXI manager interface are run-time programmable. An interrupt line reports FIFO/buffer threshold crossings, with masking and clearing via dedicated CSRs.

Raw or wrapped PCM data format is also selectable at run time. Raw mode packs samples contiguously across 32-bit words for maximum density. Wrapped mode aligns samples within a configurable word width to prevent boundary spanning. The PDM2PCM operates across two clock domains—a system clock for host system interaction and data output, and a PDM bit clock for serial data acquisition—bridged by a CDC synchronization unit. The system clock is asynchronous to the serial PDM clock and must be at least 2x the serial PDM clock frequency.

clock for serial data acquisition—bridged by a CDC synchronization unit. The system clock is asynchronous to the serial PDM clock and must be at least 2x the serial PDM clock frequency.

The core is delivered as lint-clean, synthesizable Verilog RTL or a targeted FPGA netlist, with a testbench achieving 100% code coverage, a bare-metal C driver, example firmware, synthesis scripts, timing constraints, and a comprehensive user guide.

PDM-to-PCM Conversion

• Mono and stereo modes with configurable polarity-to-channel mapping
• All standard audio sample rates
• OSR programmable from 32x to 256x
• 2- to 32-bit PCM output samples
• Raw-mode and Wrapped-mode PCM support

High-Fidelity Audio

• Maximum amplitude tracking for real-time clipping and headroom monitoring
• Fifth-order CIC decimation filter followed by a droop-compensation FIR filter
• Configurable high-pass filter to remove DC offset and low frequency noise
• Spreads harmonic distortion into the noise floor for improved audio quality at low input levels.

Software Configurable Options

• Digital volume control & soft mute
• Sample Rate & oversampling ratio
• PCM output format and sample width
• High pass filter coefficient
• Selectable rising or falling clock edge for channel 0

SoC System Interfaces

• CSR: AXI-Lite or APB
• Data: AXI4-Stream or AXI4 manager
• Maskable interrupt reporting FIFO/buffer overflows

• Lint-clean Verilog RTL source code or targeted FPGA netlist
• Integration testbench
• Simulation & synthesis scripts
• Comprehensive user documentation
• Bare-metal device driver