Vendor: Analog Bits Inc. Category: Clock Generator

PCIe 4-5 Ref Clock SSCG

The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…

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TSMC 2nm N2P View all specifications

Overview

The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Gen5 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments.

The PLL macro is implemented in Analog Bits’proprietary architecture that uses core and 1.2V IO devices.

With all components integrated, jitter performance and standby-power are significantly improved.

SSCG PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 24 40 100 MHz Input Frequency in Bypass Mode fBYPASS 24 161.1328125 MHz VCO Frequency FVCO 14400 15000 MHz Output Frequency FOUT 100 156.25 161.1328125 MHz Output Duty Cycle tDO 48 52 % Lock Time tLOCK 15 µs Reset Time tRESET 1 µs PLLOUT Random Filtered Phase Jitter RJPO,FILT 0.15 ps-RMS Modulation Frequency FM 30 33 kHz Modulation Depth (down-spread) DMD -5000 -1000 ppm Loop Bandwidth LBW 0.5 2 MHz Area A 0.083 sq. mm Operational Power PDIG +PANA 15 25 mW Output Load CL 100 fF Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.14 1.2 1.32 V Operational Temperature TOP -40 25 125 C

Key features

  • High performance design emphasis for meeting low jitter requirements in PCIe Gen4 & Gen5 applications
  • Implemented with Analog Bits’ proprietary LC architecture
  • Low power consumption
  • Spread Spectrum Clock Generation (SSCG) and tracking capability
  • Excellent jitter performance with optimized noise rejection
  • Calibration code and Bandgap voltage observability (for debug)
  • Requires no additional on-chip components or band-gaps, minimizing power consumption

Files

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Silicon Options

Foundry Node Process Maturity
TSMC 2nm N2P —

Specifications

Identity

Part Number
PCIe 4-5 Ref Clock SSCG
Vendor
Analog Bits Inc.

Provider

Analog Bits Inc.
HQ: USA
Analog Bits develops, delivers and supports industry-leading, mixed signal IP solutions. The current product portfolio includes energy-efficient and low-area SERDES, PVT sensors, ultralow-jitter clocks, memory interfaces and I/O’s, available on every mainstream manufacturing process. Customers’ applications span a wide range including: high-volume consumer products, energy-efficient servers and advanced telecommunications equipment - all leveraging Analog Bits’ highly differentiated IP products. Founded in 1995, Analog Bits, Inc. has become the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Our products include precision clocking macros such as PLLs & DLLs, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s as well as specialized memories such as high-speed SRAMs and TCAMs. With billions of IP cores fabricated in customer silicon, from 0.35-micron to 14-nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
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Frequently asked questions about Clock Generator IP cores

What is PCIe 4-5 Ref Clock SSCG?

PCIe 4-5 Ref Clock SSCG is a Clock Generator IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Clock Generator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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