ORAN Verification IP

The SmartDV's ORAN Verification IP is fully compliant with ORAN Specification V6.0 and IEEE 802.3 specifications. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

ORAN Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

ORAN Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Compliant with ORAN Specification V6.0.
• Complete ORAN Tx/Rx functionality.
• Supports O-RU and O-DU
• Supports the below encapsulation
  • Ethernet encapsulation
  • IP/UDP encapsulation
• Supports the following Transport Headers
  • eCPRI header
  • RoE header
• Supports fragmentation in the below layers
  • Application layer
  • Radio Transport layer (eCPRI or IEEE 1914.3)
• Supports the below protocols
  • C plane
  • U plane
  • S plane
  • M plane
• Supports CTI Message Protocol
• Supports the below eCPRI message types
  • IQ data message
  • Real-time control data message
  • Delay measurement message
• Supports 10G/25G/40G/50G/100G/200G/400G Ethernet Speeds
• Supports insertion of scrambler errors.
• Glitch insertion and detection.
• Supports all types of TX and RX errors insertion/detection at each layer.
  • Under and oversize frame.
  • CRC errors
  • Framing errors
  • Pause frame errors
  • Disparity and Auto-negotiation errors
  • Invalid code group insertion
  • Invalid /K/ characters insertion
  • Lane Skew insertion
  • Invalid AN sequence error insertion
  • Missing /K/ characters for packet boundries.
• Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Status counters for various events on bus.
• Supports bus accurate timing and timing checks.
• Callbacks in TX, RX and Monitor for user processing of data.
• ORAN Verification IP comes with complete test suite to test every feature of ORAN specification.
• Functional coverage for complete ORAN feature

• Faster testbench development and more complete verification of ORAN designs.
• Easy to use command interface simplifies testbench control and configuration of TX,RX and Monitor.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the ORAN testcases.
• Examples showing how to connect various components, and usage of TX,RX and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation contains User's Guide and Release notes.