Vendor: Dolphin Semiconductor Category: ROM

Metal programmable ROM compiler - Non volitile memory optimized for low power - compiler range up to 256 k

Metal programmable ROM compiler - TSMC 130 nm BCD Plus - Non volatile memory optimized for low power - compiler range up to 256 k

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Overview

Metal programmable ROM compiler - TSMC 130 nm BCD Plus - Non volatile memory optimized for low power - compiler range up to 256 k

Key features

  • For nominal voltage characterization corner
  • Power reduction features
  • Up to 50% gain in dynamic power consumption compared to standard ROM
  • Decrease of fabrication costs
  • Via 1 programmable ROM
  • 20% gain in density compared to standard ROM
  • Ultra low leakage
  • No leakage in memory plane
  • Minimal leakage in memory periphery
  • Easy Integration
  • Depending on memory capacity up to 5 different MUX options can be selected
  • High flexibility for address range and data range
  • Compliance with TSMC IP 9000 qualification process

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
sROMet-CASSIOPEIA-LLA_TSMC_130nm_BCDPlus
Vendor
Dolphin Semiconductor

Provider

Dolphin Semiconductor
HQ: France
Dolphin Semiconductor is a leading provider of semiconductor IP solutions, specializing in mixed signal IP design targeting markets such as Industrial, High-Performance Computing, Consumer Electronics, IoT and Automotive. Dolphin Semiconductor cutting-edge technology IPs in power management, high-quality audio, power metering, and design safety/robustness, allow their customers to accelerate design cycles, foster faster time-to-market and build products that address the challenges of any industry and support a more sustainable world. With a customer-centric approach, Dolphin Semiconductor provides exceptional support for successful project outcomes.
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Learn more about ROM IP core

An MLC ROM With Inserted Redundancy and Novel Sensing Scheme

An Nor-type MLC ROM, Multi Layer Cell Read Only Memory macro of 16M bits (actual 32M bits) density is presented. The MLC ROM is designed by a 0.090 μm CMOS logic process. The ROM cell of 0.40μm ×0.50μm with 0.03μm per step of the channel width and channel length increase is determined to obtain 4 levels of Ids. A scheme of 2-step sensing with current-to-voltage converter (step1) and an ADC (step2) are applied to obtain an access time of 5 ns. 4 bits per cell can be achieved by inserting more referencing columns of ROM cells to track and to compensate noise from power and ground bouncing.

A Flexible, Field-programmable ROM Replacement

For large amounts of on-chip code and data, mask read-only memory (ROM) provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field. Antifuse one-time programmable (OTP) provides a flexible, field-programmable alternative to ROM. An antifuse-based bit cell uses controlled, irreversible thin (gate) oxide breakdown to program a bit.

Heterogeneous Multicore using Cadence IP

This blog presents a heterogeneous multicore system built with the RISC-V Host CPU and Cadence IP: Xtensa DSPs, and the Janus Network-on-Chip (NoC). While this example uses an RISC-V CPU, any other ISA with similar capabilities can also serve as the host CPU.

Frequently asked questions about ROM IP cores

What is Metal programmable ROM compiler - Non volitile memory optimized for low power - compiler range up to 256 k?

Metal programmable ROM compiler - Non volitile memory optimized for low power - compiler range up to 256 k is a ROM IP core from Dolphin Semiconductor listed on Semi IP Hub.

How should engineers evaluate this ROM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ROM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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