M8052 8-bit Microcontroller

The M8052 is a straightforward implementation of an 8-bit microcontroller and is clock for clock compatible with the classic Intel 87C51 and 87C52 devices. To achieve this precise compatibility, this design uses a 12 clock per machine cycle architecture, featuring two memory accesses in each machine cycle. Instructions typically take either 12 or 24 clock cycles to execute. Only the multiply and divide instructions take longer, consuming 48 clock cycles.

The M8052 is typically used in applications that require the microcontroller core to be a drop-in replacement for a discrete 8051 device. These designs tend to be easier to adopt than optimised 8051 implementations, because they maintain precise clock cycle compatibility with older devices. Preservation of the precise clock-to-instruction ratio is often a requirement where existing software relies on timing relationships with peripheral devices such as interrupts, counters, timers etc.

The M8052 is similar to the M8051, except that the M8052 includes an additional 16-bit counter timer and has the capacity to address 256 bytes of register memory.

• Binary and clock cycle compatible with Intel 8051 designs
• Classic 12 ­clock machine cycle implementation
• Separate data and code address spaces (Harvard architecture)
• 64Kbyte program and data address spaces
• 256 byte internal data memory address space
• Support for memory banking extensions
• Optional demultiplexed program and data interfaces
• 6 ­input, two level interrupt controller
• 32 GPIO ports
• 3 16­bit counter timers
• Full­duplex serial port
• Flexible interfacing options for external peripherals
• Power saving modes: powerdown, idle and run

• The core RTL is configurable at compile time. Major configuration options include: Combined program and data address space or Harvard architecture; Code memory size; External data memory size
• Internal data memory size
• Power Management: The M8052 offers two power saving states. These are implemented by dividing the core logic into two synchronous clock domains using optional clock gates. These reduce power consumption by 75% in the idle state and to leakage levels in the powerdown state.
• Programming Support: The core runs all standard 8051 binary code. Syntill8 recommends Keil C51 compiler for code development.

• VHDL '93 and Verilog 1995 RTL source code
• RTL configuration script
• VHDL and Verilog Testbenches
• Demonstration assembly code
• Simulation scripts for Modelsim and Cadence
• Synopsys synthesis compile scripts and UCF timing constraint files
• Mentor and Synopsys DFT and ATPG scripts
• Example netlist implementation with SDF files
• Detailed product specification and a user guide containing implementation notes.