Infiniband 4X Link Protocol Engine

The Link Protocol Engine (LPE) is single core solution incorporating in Link Layer of Open System Interconnect (OSI) which significantly reduces the time and cost of implementing complex InfiniBand target system designs.

InfiniBand is an open architecture interconnect solution to handle and resolve bottleneck of multiple I/O streams simultaneously. Silicon Cores proven Intellectual Property expertise for various Link Layer and experience in high - speed channel interconnect.

The SI19IB40 is a switch - based serial I/O interconnect architecture operating at a speed of 10 Gbps for 4X in each direction. The SI19IB40 transmits and receives all kind of InfiniBand packets and generates and inspects the 32 bit Invariant Cyclic Redundancy Check (ICRC) and 16 bit Variant Cyclic Redundancy Check (VCRC).

The SI19IB40 is capable of supporting unicast as well as multicast addressing. The Maximum Transfer Unit supported by the SI19IB40 is 4096 Bytes. It has four data VLs and one management VL. The flow control mechanism implemented in the SI19IB40 is separate for each data VL and it is not implemented for the management VL.

Product Specifications :

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL core.
• Test Bench Environment Verilog.
• Targeted FPGA Xilinx Spartan-6 / Virtex-6.
• Clock Frequency : 62.5 MHz.

Product Options :

• Adaptations : 32 bit PCI or AMBA Host Interface Possible.
• Add - ons : External Link - Phy Interface Possible (for 1X / 4X).

• Fully compliant Infiniband architecture based on Infiniband Trade Association (IBTA) 1.0.a Specifications.
• Compliance to Test Suites as provided by University of New Hampshire Inter - Operability Lab.
• Full Duplex Independent Transmit and Receive Data Path controlled by Link State Machine.
• Optimized for the use in Host and Target Channel Adapters.
• Supports all Management and Data Packets.
• Supports all Transport Services and Raw Packets.
• Four data Virtual Lanes (VL) plus Management Virtual Lane (MVL) support.
• Provides credit based Link level flow control to handle Pipelined data.
• Has a 4X (Single Link with Receive and Transmit) physical layer independent LINK - PHY Interface
• PHY Interface Data Rate for 4X is 8 GBPS LINK - PHY; 16 GBPS for Full - Duplex
• Distinct 32 bit data lines for transmit and receive.
• Supports max up to total 512 Kbytes of external buffer memory for transmit and receive.
• External Buffer memory can be fine tuned by user as per its need of application.
• Single clock domain throughout the system.

• Clock Frequency: 74.6MHz for FPGA (Standard: 62.5 MHz)

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL core.
• Test Bench Environment Verilog
•