Vendor: Noesis Technologies Category: Channel Coding

Interleaver / De-interleaver

Configurable interleaving/deinterleaving function that can be used in a wide range of applications that employ channel coding.

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TSMC 180nm BCDG2 Silicon Proven View all specifications

Overview

Configurable interleaving/deinterleaving function that can be used in a wide range of applications that employ channel coding.

Key features

  • Support for block or convolutional (de interleaving algorithm.
  • Programmable interleaving or deinterleaving functionality.
  • Parameterized symbol width and codeword length.
  • Programmable block size, number or rows/columns.
  • Programmable rows/columns permutations.
  • Programmable number of branches and branch length.
  • Compatible with continuous or burst mode Reed Solomon codecs.
  • Fully synchronous design using a single clock.

Block Diagram

ntINT_DEINT block diagram

What’s Included?

  • Synthesizable VHDL or Verilog code.
  • Comprehensive test bench.
  • Detailed user's guide.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 180nm BCDG2 Silicon Proven

Specifications

Identity

Part Number
ntINT_DEINT
Vendor
Noesis Technologies

Provider

Noesis Technologies
HQ: Greece
Noesis Technologies specializes in design,development and marketing of high quality, cost effective communication IP cores and provides expert ASIC/FPGA design services in telecom DSP area. Our solutions are key components to the most sophisticated telecom systems. Backed-up by our leading-edge expertise on forward error correction, encryption and networking technology as well as on DSP algorithm development we provide robust solutions that are used to improve data quality, increase bandwidth or reduce the overall system cost of end-application.
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Learn more about Channel Coding IP core

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Frequently asked questions about Channel Coding IP cores

What is Interleaver / De-interleaver?

Interleaver / De-interleaver is a Channel Coding IP core from Noesis Technologies listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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