Vendor: asicNorth Category: PLL

Integer N PLL for Frequency Synthesis

The ANLBPLL0100 is an integer-N PLL for frequency synthesis that can be used to create a low phase-noise local oscillator (LO) fo…

GlobalFoundries 130nm View all specifications

Overview

The ANLBPLL0100 is an integer-N PLL for frequency synthesis that can be used to create a low phase-noise local oscillator (LO) for applications operating in the L band (1 GHz – 2 GHz). The low phase noise results in ultra-low clock jitter for applications which require it. The frequency synthesizer consists of a clock receiver, phase-frequency detector, low-noise charge pump, active loop filter utilizing on-die and off-die components, multi-band LC VCO, and an LO output buffer. The frequency synthesizer uses a 9-bit programmable divider to support integer multiplication factors from 100 to 511.

Key features

  • 1 GHz–2 GHz LO frequency range
  • 5 MHz–20 MHz input clock frequency range
  • 9-bit programmable divider (100-511)
  • 7-band VCO with off-chip resonator
  • Programmable charge pump and loop filter
  • Integrated LDO regulator
  • Lock indicator
  • Process: 130nm GF BiCMOS8HP
  • Area = 2.74mm2 (1.48 mm x 1.85mm)
  • Phase Noise: -120 dBc/Hz @ 1MHz (1.5 GHz)
  • Jitter RMS: 1.2ps (12KHz-20MHz integration BW)
  • Loop bandwidth: 5 KHz-50 KHz
  • Lock time: 1ms

Block Diagram

Benefits

  • Low phase-noise applications

Applications

  • L band applications including:
  • - Satellite navigation (GPS)
  • - Mobile satellite telecommunications
  • - Aircraft surveillance
  • - Digital audio/video broadcasting
  • - Astronomy
  • - Amateur radio
  • General purpose clock synthesis

What’s Included?

  • Specification
  • GDS
  • CDL
  • LEF
  • Verilog model
  • .LIB
  • Application documentation

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 130nm 130 1300 nm

Specifications

Identity

Part Number
ANLBPLL0100
Vendor
asicNorth
Type
Silicon IP

Provider

asicNorth
HQ: USA
ASIC North is a leading VLSI design service provider specializing in enabling integrated device manufacturers (IDMs) and fabless semiconductor companies. With vast experience in CMOS circuit design, an analog-mixed-signal IP library, ASIC design capabilities and characterization services, ASIC North has the ability to create a broad of range of semiconductor-based solutions.

Learn more about PLL IP core

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Specifying a PLL Part 2: Jitter Basics

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Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Integer N PLL for Frequency Synthesis?

Integer N PLL for Frequency Synthesis is a PLL IP core from asicNorth listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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