Vendor: SmartDV Technologies Category: Smartcard

IEC7816 Slave IIP

IEC7816 Slave interface provides full support for the IEC7816 (SmartCard) synchronous serial interface, compatible with ISO/IEC 7…

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Overview

IEC7816 Slave interface provides full support for the IEC7816 (SmartCard) synchronous serial interface, compatible with ISO/IEC 7816-3 specification. Through its IEC7816 compatibility, it provides a simple interface to a wide range of low-cost devices. IEC7816 Slave IIP is proven in FPGA environment. The host interface of the IEC7816 Slave can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

IEC7816 Slave IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with ISO/IEC 7816-3 Specification.
  • Full IEC7816-3 Slave functionality.
  • Supports all functions for complete smart card sessions, including
    • Card activation and deactivation
    • Cold/warm reset
    • Answer to Reset (ATR) response reception
    • Data transfers to and from the card
  • Supports adjustable clock rate and bit (baud) rate.
  • Supports configurable automatic byte repetition.
  • Supports commonly used communication protocols
    • T = 0 for asynchronous half-duplex character transmission, and
    • T = 1 for asynchronous half-duplex block transmission
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices

Block Diagram

IEC7816 Slave IIP block diagram

Benefits

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The IEC7816 Slave interface is available in Source and netlist products.
  • The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
IEC7816 Slave IIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
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Frequently asked questions about Smartcard IP cores

What is IEC7816 Slave IIP?

IEC7816 Slave IIP is a Smartcard IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Smartcard?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Smartcard IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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