Cellular IoT and LPWAN - addressing the industry FUD
Chet Babla, ARM
Vendor:
Noesis Technologies
Category:
Cellular
High Throughput Rate OFDM Baseband PHY Processor
The ntOFDM_HS_BBP IP implements the physical layer transmission and reception processing engines of a custom subset of the 802.16…
Overview
The ntOFDM_HS_BBP IP implements the physical layer transmission and reception processing engines of a custom subset of the 802.16-2012 standard. The ntOFDM_HS_BBP IP core main functional blocks are the Transmitter, the Receiver, the Register File and High Level Controller and the Analog Front End interface. The User programs the Register file in order to define the systems functionality, configure control parameters, and define the desired modes of operation. The Analog Front End interface module connects the ntOFDM_HS_BBP produced sample rate to the any AFE board with all the appropriate rate conversions.
The Transmitter includes the Bit Level Processing Block (BLPB) and the Symbol Level Processing Block (SLPB). The BLPB operates on Users/Bursts payload bytes and uses Scrambling, FEC encoding, Interleaving and Symbol Modulation to produce I/Q modulated symbols. The SLPB operates on the produced symbols and uses them to generate the OFMDA-Symbol stream, inserts pilots and guard intervals, transforms the signal to the time domain (FFT transform) and adds the Cyclic Prefix.
The Receiver includes the Synchronizer, the SLPB and the BLPB main processing blocks. The Synchronizer searches for a known pattern (Preamble) in an effort to detect the exact start of a new incoming frame. It applies STO and CFO corrections on the signal. The SLPB operates on the synchronized signal and tries to compensate the channel impairments applied on the signal, while bringing it back to the frequency domain. It also demodulates the OFMDA symbols back to data symbols and provides them to the BLPB. The BLPB RX implements the exact op-posite procedure to the BLPB TX and recovers the corrected Users/Bursts payload bytes.
A real-time demonstration video of ntOFDM_HS_BBP IP Core can be downloaded from
http://www.noesis-tech.com/downloads/OFDM_Demo.mp4
The Transmitter includes the Bit Level Processing Block (BLPB) and the Symbol Level Processing Block (SLPB). The BLPB operates on Users/Bursts payload bytes and uses Scrambling, FEC encoding, Interleaving and Symbol Modulation to produce I/Q modulated symbols. The SLPB operates on the produced symbols and uses them to generate the OFMDA-Symbol stream, inserts pilots and guard intervals, transforms the signal to the time domain (FFT transform) and adds the Cyclic Prefix.
The Receiver includes the Synchronizer, the SLPB and the BLPB main processing blocks. The Synchronizer searches for a known pattern (Preamble) in an effort to detect the exact start of a new incoming frame. It applies STO and CFO corrections on the signal. The SLPB operates on the synchronized signal and tries to compensate the channel impairments applied on the signal, while bringing it back to the frequency domain. It also demodulates the OFMDA symbols back to data symbols and provides them to the BLPB. The BLPB RX implements the exact op-posite procedure to the BLPB TX and recovers the corrected Users/Bursts payload bytes.
A real-time demonstration video of ntOFDM_HS_BBP IP Core can be downloaded from
http://www.noesis-tech.com/downloads/OFDM_Demo.mp4
Key features
- Custom OFDMA system based on 802.16e standard features.
- Complete Back-end User IF for primitive MAC integration.
- RTL driver and interfacing logic to C driver are provided.
- Single User Burst (Point to Point) or Multi User Bursts (Point to Multi-point)
- Frames functional configurability.
- Detailed fixed-point bit-true Matlab model, with built in configuration guide for the RTL register file.
- DL transmission (TX) and UL reception (RX) locked stations.
- Optional generation of Transmitter only, Receiver only or both instances inside the same top level ntOFDM_HS_BBP architecture in order to provide flexibility and support TDD or FDD scenarios of operation.
- Wide range of Code Rates and Modulation levels combinations preconfigured in 14 modes of operation, selectable per User burst.
- FEC employs various combinations of Convolutional Codes, Reed Solomon codes, puncturing and repetition encoding to produce the overall code rate.
- Programmable FFT transform size [128, 256, 512, 1024, 2048].
- Programmable Cyclic Prefix size [1/4, 1/8, 1/16, 1/32].
- Programmable digital boosting.
- DL FUSC subcarriers permutation.
- Custom Preamble, Frame Control Header (FCH) and shared users MAP. OFDM symbols overhead, with separate CRC-16 checks.
- DSP engine payload throughput up to 400Mbps, for 70Mhz back end system clock, prior to Preamble, FCH and MAP overheads.
- Optional separate double-buffered RF TX/RX buffers for clock rate adaptation to any RF/Bandwidth clock rate.
- Synchronizer and SLPB RX blocks detect and correct STO, fractional and integer CFO, as well as small phase errors.
- IP reports estimated channel SNR per pilot tone prior to Channel Estimation function in Receiver
- IP reports estimated fractional Carrier Frequency Offset.
- Interrupts outputs indicating buffers overflow errors, synchronization events, successful or failed CRC checks.
Block Diagram
ntOFDM_HS_BBP block diagram
Applications
- The ntOFDM_HS_BBP core can be used in a variety of customized point to point or point to multipoint applications.
What’s Included?
- Fully commented synthesizable VHDL/Verilog source code or FPGA netlist.
- VHDL/Verilog test bench and example configuration files.
- Matlab model.
- Comprehensive technical documentation.
- Technical support.
Video
A high throughput rate OFDM Baseband PHY IP Core for wireless applications
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
ntOFDM_HS_BBP
Vendor
Noesis Technologies
Provider
Noesis Technologies
HQ:
Greece
Noesis Technologies specializes in design,development and marketing of high quality, cost effective communication IP cores and provides expert ASIC/FPGA design services in telecom DSP area.
Our solutions are key components to the most sophisticated telecom systems. Backed-up by our leading-edge expertise on forward error correction, encryption and networking technology as well as on DSP algorithm development we provide robust solutions that are used to improve data quality, increase bandwidth or reduce the overall system cost of end-application.
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Frequently asked questions about cellular IP cores
What is High Throughput Rate OFDM Baseband PHY Processor?
High Throughput Rate OFDM Baseband PHY Processor is a Cellular IP core from Noesis Technologies listed on Semi IP Hub.
How should engineers evaluate this Cellular?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Cellular IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.