Vendor: asicNorth Category: PLL

Fractional-N Frequency Synthesizer (PLL)

The ANFNPLL0100 is a fractional-N frequency synthesizer that can be used to implement local oscillator (LO) in the low power, low…

Contact Provider Request Datasheet
GlobalFoundries 130nm View all specifications

Overview

The ANFNPLL0100 is a fractional-N frequency synthesizer that can be used to implement local oscillator (LO) in the low power, low data rate, wireless applications such as ZigBee, Bluetooth Low Energy (LE). The frequency synthesizer consists of low noise phase frequency detector (PFD), a precision
charge pump, an internal loop filter, and dual band voltage controlled oscillator (VCO). The frequency synthesizer has 5-bit programmable divider
supporting integer multiplication up to 63, and 3rd order sigma-delta modulator supporting 20-bit fractional resolution.

Key features

  • 2.48 GHz Fractional-N Frequency
  • 1.2 V Power Supply
  • Programmable Charge Pump Current
  • Programmable VCO Current Limit
  • Built-in VCO Coarse Tune Calibration
  • 5 Bit Programmable Divider
  • 3rd Order Sigma Delta Modulator supporting 20 Bit Fractional Resolution
  • Integrated Loop Filter
  • Process: 130nm GF CMOS8RF
  • Area = 0.66 mm2 (0.70 mm x 0.95mm)

Block Diagram

ANFNPLL0100 block diagram

Benefits

  • Phase Noise:
    • -110 dBc/Hz (2.48GHz at 1MHz offset)
  • Lock Time: 5 us
    • TX Frequency Range: 2402 MHz – 2483.5 MHz
    • RX Frequency Range: 1921.6 MHz – 1986.8 MHz

Applications

  • Wireless Application:
  • - Bluetooth LE, ZigBee
  • Wireless Meter Reading
  • Test and Measurement
  • Clock Generation

What’s Included?

  • Specification
  • GDS
  • CDL
  • LEF
  • Verilog Model
  • .LIB

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 130nm 130 1300 nm —

Specifications

Identity

Part Number
ANFNPLL0100
Vendor
asicNorth
Type
Silicon IP

Provider

asicNorth
HQ: USA
ASIC North is a leading VLSI design service provider specializing in enabling integrated device manufacturers (IDMs) and fabless semiconductor companies. With vast experience in CMOS circuit design, an analog-mixed-signal IP library, ASIC design capabilities and characterization services, ASIC North has the ability to create a broad of range of semiconductor-based solutions.
Contact asicNorth

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Fractional-N Frequency Synthesizer (PLL)?

Fractional-N Frequency Synthesizer (PLL) is a PLL IP core from asicNorth listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP