Fast NIST ESV certified, FIPS (SP800-90A/B/C) True Random Number Generator
The TRNG-IP-77 is a FIPS-compliant and certified IP core for True Random Number Generation (TRNG) with an optional post-processor…
Overview
The TRNG-IP-77 is a FIPS-compliant and certified IP core for True Random Number Generation (TRNG) with an optional post-processor and several internal self-tests. Designed for easy integration into ASICs and SOCs, the 100% digital standard cell based TRNG-IP-77 provides a reliable and cost-effective embedded IP solution for our customer’s SoCs.
How the TRNG-IP-77 works
TRNGs are typically deployed in semiconductors for securing data communications, electronic transactions, and data storage. They are used for generation of keys, initialization vectors, cookies, and nonces.
Additionally, TRNGs can also be used for statistical sampling, communications protocol timers, as well as noise generation. The TRNG-IP-77 implements a self-timed digital oscillator circuit using rule-30 elements that causes voltage transitions to proceed bi-directionally around a ring.
This patent-protected TRNG implementation has all the noise-accumulation benefits of traditional free-running oscillators, but also adds non-traditional source of entropy: a bi-directional ring of chaotic pattern generators. This novel ring topology creates bi-directional constructive/destructive interference of the waveform, resulting in very fast time-to-max-entropy, and very high entropy generation rates. Compared to free running oscillator-based entropy sources, this RBG core has other advantages such as inherent resistance to simple noise injection locking, and minimized need for oscillator calibration and/or noise isolation during implementation.
The TRNG-IP-77 is a security aware design:
- SP 800-90B entropy source, digital 2-ring Chaotic Random Number Generator.
- SP 800-90A AES CTR mode based post processing
- Selectable reseed interval
- Built-in health tests
The TRNG-IP-77 is compliant with Federal Information Processing Standards (FIPS) Publication 140-3, facilitating system certification. The design is compliant with the latest versions for NIST SP800-90A/B/C. A NIST SP800-90A Deterministic Random Bit Generator (DRBG) is available for the required post processing. The TRNG-IP-77 is ESV certified and is FIPS-approved when integrated into Rambus Root of Trust solutions.
The TRNG-IP-77 is silicon proven, and its flexible, layered design makes it easy to integrate into SoCs.
Key features
- Non-deterministic Random Number Generator, FIPS-140 SP800-90A/B compliant, ESV certified for NRBGs and DRBGs (#E225).
- High performance, low power, fully digital, standard cell only, supports all CMOS nodes.
- Available as standalone RBG or embedded in the Rambus RT-130, RT-630, RT-660 Root of Trusts
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Random Number Generator IP core
Rambus CryptoManager Root of Trust Solutions Tailor Security Capabilities to Specific Customer Needs with New Three-Tier Architecture
Rambus True Random Number Generator Certified to NIST SP 800-90B Standard
How random is random?
The Silent Guardian of AI Compute - PUFrt Unifies Hardware Security and Memory Repair to Build the Trust Foundation for AI Factories
A Comprehensive Post-Quantum Cryptography (PQC) Solution based on Physical Unclonable Function (PUF)
Frequently asked questions about Random Number Generator IP cores
What is Fast NIST ESV certified, FIPS (SP800-90A/B/C) True Random Number Generator?
Fast NIST ESV certified, FIPS (SP800-90A/B/C) True Random Number Generator is a Random Number Generator IP core from Rambus, Inc. listed on Semi IP Hub.
How should engineers evaluate this Random Number Generator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Random Number Generator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.