Vendor: Creonic Category: Channel Coding

DVB-S2X LDPC/BCH Decoder

The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on FPGAs.

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Overview

The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on state-of-the-art FPGAs. DVB-S2X is the next generation satellite transmission standard which is an extended version of its well-established predecessor DVB-S2. The new specification allows for spectral efficiency gains of up to 50% by offering lower roll-off factors, higher modulations and a finer code rate granularity compared to DVB-S2.

Key features

  • Compliant with DVB-S2 and DVB-S2X
  • Support for decoding of BBFRAMEs
  • Support for ACM, CCM, and VCM
  • Support for very low SNR modes (VLSNR) with SNRs below -9 dB
  • Support for short, medium, and normal frames (16,200 bits, 32,400 and 64,800 bits)
  • Support for BPSK, QPSK, 8-PSK, 16-APSK, 32-APSK, 64-APSK, 128-APSK, and 256-APSK

Block Diagram

CREONIC CODING DVB S2X block diagram

Benefits

  • Validated against 3rd party DVB-S2X modulators
  • Silicon-proven IP core
  • Based on industry-proven design for DVB-S2
  • Soft-Decision demapper, block deinterleaver, LDPC decoder, BCH decoder, descrambler, and CRC checks included
  • Low-power and low-complexity design
  • Frame-to-frame on-the-fly configuration
  • Design-time configuration of throughput for optimal resource utilization
  • Faster convergence due to layered LDPC decoder architecture
  • Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy
  • Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance with on-the-fly selection in ACM/VCM modes
  • Collection of statistics (error rates, average number of iterations, signal-to noise ratio (SNR))
  • Available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip)
  • Deliverable includes VHDL source code or synthesized netlist, HDL simulation models, VHDL or SystemC testbench, and bit-accurate Matlab, C or C++ simulation model

Applications

  • Satellite communication
  • Applications with the highest demands on forward error correction
  • Applications with the need for a wide range of code rates (1/10 to 9/10)

What’s Included?

  • VHDL source code or netlist
  • HDL simulation models
  • VHDL or SystemC testbench
  • Bit-accurate Matlab, C or C++ simulation model
  • Comprehensive documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
CREONIC CODING DVB S2X
Vendor
Creonic
Type
Silicon IP

Provider

Creonic
HQ: Germany
Creonic is an ISO 9001:2015 certified provider of ready-for-use IP cores for wired, wireless, fiber, and free-space optical communications. All relevant digital signal processing algorithms are covered, including, but not limited to, forward error correction, modulation, equalization, and demodulation. The company offers the richest product portfolio in this field, covering standards like 3GPP 5G, DVB-S2X, DVB-RCS2, CCSDS, andWiFi. The products are applicable for ASIC and FPGA technologies and comply with the highest requirements with respect to quality and performance. For more information, please visit our website at www.creonic.com .
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Learn more about Channel Coding IP core

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Frequently asked questions about Channel Coding IP cores

What is DVB-S2X LDPC/BCH Decoder?

DVB-S2X LDPC/BCH Decoder is a Channel Coding IP core from Creonic listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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