Digital PUF IP
Small footprint trusted identity Generate unclonable 128 or 256-bit seeds with a compact, logic-based PUF that drops into any SoC.
Overview
Small footprint trusted identity
Generate unclonable 128 or 256-bit seeds with a compact, logic-based PUF that drops into any SoC. Digital PUF IP adds true hardware identity for secure boot, key generation, and device authentication with minimal silicon overhead.
Whether you design silicon, architect security, or validate compliance, Digital PUF IP delivers the trust anchor you need
- SoC & ASIC Designers
Add hardware identity and key‐seed generation without large area or external fuses. - Security Architects
Tie secure boot and root-of-trust schemes to a physically unclonable seed. - Embedded Platform Engineers
Pair with TRNG or secure-element blocks for complete crypto workflows. - Compliance & QA Teams
NIST-validated entropy and health tests simplify certification and audit.
Key features
Unclonable Identity
Each device derives a unique, tamper-resistant seed for authentication and key generation
Customisable Security
Choose 128- or 256-bit seeds to match application requirements and crypto policies
Low Silicon Footprint
<30 kGates (typical) including fuzzy extractor
Layout-Hardened Reliability
Optimised logic cells reduce silicon skew and improve bit stability
Standards Validated
Randomness validated against NIST SP800, including CQ’s PUF-appropriate TurRiNG test suite and BSI’s AIS31 test suites
Easy SoC Integration
APB or AXI interface options drop into existing bus architectures
Benefits
Logic-Based Entropy Array
Static mismatch in logic cells produces a high-entropy bitstring that is unique per device
Fuzzy Extractor & Helper Data
Built-in error-correction logic creates helper data for repeatable seed regeneration with 1 × 10⁻⁹ failure rate
NIST-Validated Randomness
Raw entropy and post-correction output meet SP 800-22 and SP 800-90B requirements
Configurable Seed Size
Select 128-bit or 256-bit output to align with AES, ECC, or PQC key strengths
Hardened Physical Design
Layout guidelines and optional skew-reduction techniques improve robustness across technology nodes
Custom Bus Interface
APB by default; AXI or proprietary bus options available for seamless SoC connectivity
Video
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 55nm | 55 550 nm | Silicon Proven |
Specifications
Identity
Provider
Learn more about PUF IP core
ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
Why SRAM PUF Technology Is the Bedrock of Dependable Security in Any Chip
Combining Root of Trust and PUF Technology For Robust Chip Security
Basics of SRAM PUF and how to deploy it for IoT security
The Four Angles of Examining PUF
Frequently asked questions about PUF IP cores
What is Digital PUF IP?
Digital PUF IP is a PUF IP core from Crypto Quantique listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.
How should engineers evaluate this PUF?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PUF IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.