VeriSilicon SMIC 0.11μm 1.2V/3.3V DUPIO_01 Library
Overview
VeriSilicon SMIC 0.11μm 1.2V/3.3V DUP I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.11μm (0.13μm 90% direct shrink)Logic 1P8M Salicide 1.2/3.3V process. This library supports Device Under Pad (DUP). This library includes analog I/O cell part and digital I/O cell part, and the digital I/O cells can take 5V tolerance and work with configurable and variable driving strength between 2mA - 24mA. This library supports Inline I/O pad.
Key Features
- SMIC 0.11μm Logic 1P8M Salicide 1.2V/3.3V process
- Low area and low cost design using DUP technique
- 1.2V core power, 3.3V IO, digital IO supports 5V tolerance
- This library includes analog I/O cell part
- Configurable output driving capability with different slew rate
- Supports configurable pull up and pull down resistor
- Supports both CMOS input and Schmitt input with LVTTL compatible
- Provides 2Mhz ~ 27Mhz OSC IO cell
- Suitable for six, seven, or eight metal layers of physical design
- Competitive pad pitch and height
Deliverables
- Databook in electronic form
- Verilog models and Synopsys synthesis models
- Cadence Silicon Ensemble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
Technical Specifications
Foundry, Node
SMIC 0.11um
SMIC
Pre-Silicon:
110nm
G
Related IPs
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- VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
- VeriSilicon SMIC 0.13μm 1.2V/3.3V VPPIO_DUP_01 IO Library
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