High bit rate Turbo Decoder core for 3GPP LTE/ LTE A

Overview

Key Features

• 3GPP LTE/ LTE Advanced (LTE A) specification complaint
• Implements decoder for requirements as defined in Section 5.1.3.2 of the specification [1]
• Highly parallel and hardware efficient architecture
• Supports all code block sizes i.e., 40 – 6144
• Programmable number of iterations in half iteration step
• Support for Rate 1/3 coded output
• Programmable parallelism. Option for 1,2,4,8 MAP decoders in parallel.
• De-rate matching block can be optionally included
• Employs state metric propagation to improve performance of the decoder for high coding rates
• Easy interface definition.
• Customization to AXI or Avalon bus interface supported.
• Bit accurate C and MATLAB models available for RTL test vector generation.
• HARQ feature support

Benefits

• High throughput rates are supported with this implementation and is easily customizable for area/ throughput tradeoffs.
• Supports CRC computation, HARQ feature support.
• The Lekha Turbo IP core alongwith few other functions is also available packaged as a bit rate co-processor. This solution helps system designers to either use this in conjunction with a DSP or in stand alone mode on a FPGA.

Block Diagram

Applications

• Wireless Communications
• LTE/ LTE A UE Equipment
• Forward Error Correction blocks

Deliverables

• Licensable in Netlist or Verilog or VHDL source format
• Target technology – Xilinx, Altera, Lattice devices
• Test bench
• MATLAB, C, VHDL, Verilog simulation models available
• Detailed technical documentation

Technical Specifications