ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15
Very high throughput (>20 Gbps) LDPC decoder and encoder for 3GPP 5G Release 15.
Overview
Very high throughput (>20 Gbps) LDPC decoder and encoder for 3GPP 5G Release 15. It supports both base-graphs, and all rates.
Key features
- Portable to all ASIC and FPGA technologies
What’s Included?
- 1) Simulation bit-exact shared-object for Matlab/Octave/C/Cpp
- 2) Synthesizable Verilog HDL code
- 3) HDL test bench with vectors
- 4) Integration guidelines and datasheet
- 5) Support
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Channel Coding IP core
Altera purchases optical network IP vendor Avalon Microelectronics
FAUST: On-Chip Distributed SoC Architecture for a 4G Baseband Modem Chipset
Satellite modems structure Internet access
Audio Transport in DisplayPort VIP
Extending the SoC Architecture of 3G terminal to Multimedia Applications
Frequently asked questions about Channel Coding IP cores
What is ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15?
ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15 is a Channel Coding IP core from Continuous-bits Ltd. listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.