Very high throughput (>20 Gbps) LDPC decoder and encoder for 3GPP 5G Release 15. It supports both base-graphs, and all rates.
ASIC IP-core for very-high-throughput decoding (>20G) of 3GPP 5G Release 15
Overview
Key Features
- Portable to all ASIC and FPGA technologies
Deliverables
- 1) Simulation bit-exact shared-object for Matlab/Octave/C/Cpp
- 2) Synthesizable Verilog HDL code
- 3) HDL test bench with vectors
- 4) Integration guidelines and datasheet
- 5) Support
Technical Specifications
TSMC
Pre-Silicon:
10nm
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