Vendor: StarFive Category: Vector Processor

CPU IP Following the RVA23 Profile, supporting RVV1.0 and all extensions of Vector Crypto

Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH,…

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Overview

Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH, supports RVV1.0 and supports all extensions of Vector Crypto. With a score of 8.5 SPECInt2006/GHz, Dubhe-83 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive. Dubhe-83 has been pre-integrated and verified, making it easy to use for SoC development work. With options of single-core, dual-core, or quad-core in a single cluster with memory coherency, Dubhe-83 is highly scalable.

Key features

  • SPECint2006:8.5/GHz
  • Dhystone：6.0/MHz（Legal）
  • RV64GCBVH
  • 10+ stage, 5-issue pipeline
  • Superscalar, Deep Out-of-Order Execution
  • Multi-Core Cache Coherence Support

Block Diagram

Dubhe-83 block diagram

Applications

Mobile Applications

  • Smartphones
  • Tablets
  • Smart wearables
  • Gaming devices

Industrial Control

  • HMI
  • Industrial display
  • Industrial inspection
  • Smart gateways

AI

  • Robotics
  • Computer Vision
  • Smart home

Specifications

Identity

Part Number
Dubhe-83
Vendor
StarFive
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

StarFive
HQ: China
Contact StarFive

Learn more about Vector Processor IP core

MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference

Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural networks. From this trend arises the need for high-performance hardware exhibiting predictable timing behavior. While state-of-the-art real-time hardware often suffers from limited memory and compute resources, modern AI accelerators typically lack the crucial predictability due to memory interference. The authors present a new hardware architecture to bridge this gap between performance and predictability.

Integrating eFPGA for Hybrid Signal Processing Architectures

As system requirements evolve toward multi-standard, reconfigurable platforms, signal processing architectures are under pressure to deliver both ASIC-class performance and software-like flexibility. Semiconductor engineers face a fundamental tradeoff: fixed logic yields, unmatched throughput, and efficiency, but cannot adapt once taped out. Software-programmable solutions offer flexibility but often miss hard real-time performance constraints and can consume more power.

FeNN-DMA: A RISC-V SoC for SNN acceleration

Spiking Neural Networks (SNNs) are a promising, energy-efficient alternative to standard Artificial Neural Networks (ANNs) and are particularly well-suited to spatio-temporal tasks such as keyword spotting and video classification. However, SNNs have a much lower arithmetic intensity than ANNs and are therefore not well-matched to standard accelerators like GPUs and TPUs. Field Programmable Gate Arrays (FPGAs) are designed for such memory-bound workloads and here we develop a novel, fully-programmable RISC-V-based system-on-chip (FeNN-DMA), tailored to simulating SNNs on modern UltraScale+ FPGAs.

Frequently asked questions about Vector Processor IP cores

What is CPU IP Following the RVA23 Profile, supporting RVV1.0 and all extensions of Vector Crypto?

CPU IP Following the RVA23 Profile, supporting RVV1.0 and all extensions of Vector Crypto is a Vector Processor IP core from StarFive listed on Semi IP Hub.

How should engineers evaluate this Vector Processor?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Vector Processor IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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