Overview
Building on the highly popular SiFive Intelligence™ X280 products’ success in AI/ML applications across mobile, infrastructure and automotive applications, where they are frequently coupled to hardware accelerators, the X390 brings a 4x improvement to vector computation with its single core configuration, doubled vector length and dual vector ALUs.
This allows 4x the sustained data bandwidth while calling on the quad core configuration. With SiFive VCIX. companies can easily add their own vector instructions and/or acceleration hardware, bringing unprecedented flexibility and allowing them to greatly increase performance with custom instructions.
Learn more about Vector Processor IP core
See how Codasip Studio enables SYCLOPS to implement a customizable RISC-V Vector processor, accelerating the future of open-source, high-performance AI compute at the Edge.
Real-time systems, particularly those used in domains like automated driving, are increasingly adopting neural networks. From this trend arises the need for high-performance hardware exhibiting predictable timing behavior. While state-of-the-art real-time hardware often suffers from limited memory and compute resources, modern AI accelerators typically lack the crucial predictability due to memory interference. The authors present a new hardware architecture to bridge this gap between performance and predictability.
Scalable IP Core of Vector Stream Cipher
As system requirements evolve toward multi-standard, reconfigurable platforms, signal processing architectures are under pressure to deliver both ASIC-class performance and software-like flexibility. Semiconductor engineers face a fundamental tradeoff: fixed logic yields, unmatched throughput, and efficiency, but cannot adapt once taped out. Software-programmable solutions offer flexibility but often miss hard real-time performance constraints and can consume more power.
Spiking Neural Networks (SNNs) are a promising, energy-efficient alternative to standard Artificial Neural Networks (ANNs) and are particularly well-suited to spatio-temporal tasks such as keyword spotting and video classification. However, SNNs have a much lower arithmetic intensity than ANNs and are therefore not well-matched to standard accelerators like GPUs and TPUs. Field Programmable Gate Arrays (FPGAs) are designed for such memory-bound workloads and here we develop a novel, fully-programmable RISC-V-based system-on-chip (FeNN-DMA), tailored to simulating SNNs on modern UltraScale+ FPGAs.
Much like the human visual system, embedded computer vision systems perform the same visual functions of analyzing and extracting information from video in a wide variety of products.
