Vendor: Noesis Technologies Category: Channel Coding

Configurable Viterbi Decoder

configurable Viterbi Decoder compliant with the requirements of nearly all modern standards using Viterbi error correction.

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TSMC 180nm BCDG2 Silicon Proven View all specifications

Overview

Highly configurable Viterbi Decoder compliant with the requirements of nearly all modern standards using Viterbi error correction.

Key features

  • Support for zero-tail and tail-biting Viterbi decoding algorithms.
  • Configurable constraint length.
  • Configurable trace-back depth.
  • Configurable code rate and soft bits.
  • Continuous or gapped input data streams.
  • Fully parallel or resource based architectures for different gate count/speed combinations.
  • Low decoder latency.
  • Fully synchronous design using a single clock.

Block Diagram

ntVIT block diagram

What’s Included?

  • Synthesizable VHDL or Verilog code.
  • C++ model for system simulation.
  • Comprehensive test bench.
  • Detailed user's guide.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 180nm BCDG2 Silicon Proven

Specifications

Identity

Part Number
ntVIT
Vendor
Noesis Technologies

Provider

Noesis Technologies
HQ: Greece
Noesis Technologies specializes in design,development and marketing of high quality, cost effective communication IP cores and provides expert ASIC/FPGA design services in telecom DSP area. Our solutions are key components to the most sophisticated telecom systems. Backed-up by our leading-edge expertise on forward error correction, encryption and networking technology as well as on DSP algorithm development we provide robust solutions that are used to improve data quality, increase bandwidth or reduce the overall system cost of end-application.
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Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

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Frequently asked questions about Channel Coding IP cores

What is Configurable Viterbi Decoder?

Configurable Viterbi Decoder is a Channel Coding IP core from Noesis Technologies listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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