Vendor: Frontgrade Gaisler Category: Bus Fabric

Configurable AMBA bus SoC platform

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development.

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Overview

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.

 

Key features

  • Robust and fully synchronous single-edge clock designs
  • Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
  • Fault-tolerant and SEU-proof version
  • Symmetric Multi-processor support (SMP)
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors
  • IP cores:
  • LEON3 processor,SPARC V8 instruction set with V8e extensions
  • Hardware multiply, divide and MAC units
  • Local instruction and data scratch pad rams
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • AMBA controller with round robin arbiter
  • AMBA to APB bridge
  • AHB to AHB bridge
  • Advanced on-chip debug support with instruction and data trace buffer
  • Fully pipelined IEEE-754 FPU
  • SRAM, SDRAM and DDR controllers
  • 32-bit Master/Target PCI
  • 10/100/1000 Ethernet MAC
  • CAN interface
  • SpaceWire interface
  • Mil-std-1553 interface
  • Advanced Encryption Standard (AES)
  • Elliptic Curve Cryptograph (ECC)
  • ATA Controller
  • VGA Controller
  • PS2 and keyboard
  • GPIO
  • Timers
  • UARTs
  • Interrupt controller

Benefits

  • Available in GPL for evaluation
  • Low cost commercial license
  • Easily prototyped on low-cost FPGA boards
  • Low area

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
GRLIB
Vendor
Frontgrade Gaisler

Provider

Frontgrade Gaisler
HQ: Sweden
Cobham Gaisler provides IP cores and supporting development tools for embedded processors based on the SPARC architecture. The key product is the LEON synthesizable processor model together with a full development environment and a library of IP cores (GRLIB). Our personnel have extended design experience, and have been involved in establishing European standards for ASIC and FPGA development. Aeroflex Gaisler has a long experience in the management of ASIC development projects, and in the design of flight quality microelectronic devices. The company specializes in digital hardware design (ASIC/FPGA) for both commercial and aerospace applications.
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Frequently asked questions about On-Chip Bus IP cores

What is Configurable AMBA bus SoC platform?

Configurable AMBA bus SoC platform is a Bus Fabric IP core from Frontgrade Gaisler listed on Semi IP Hub.

How should engineers evaluate this Bus Fabric?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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