Vendor: Global IP Core Sales Category: Channel Coding

CCSDS AR4JA LDPC Decoder & Encoder

The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding diff…

Contact Provider Request Datasheet

Overview

The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain high throughput, two different levels of parallelism are carried out; 128 check nodes and 6 variable nodes which are processed at the same time. Pipeline architecture is followed which significantly speeds up the whole decoding process. Also, layered architecture is implemented which helps to enhance the speed of the decoding process. AR4JA LDPC decoder supports soft decision decoding and hard decision output.

Key features

  • CCSDS AR4JA LDPC Code family is quasi-cyclic  
  •  Irregular parity check matrix 
  • Run time configuration for more than one code rate (i.e., 1/2,  2/3, 3/4) 
  • Configurable codeword size that supports 2K, 3K, and 4K information words  
  • Minimum sum algorithm  
  • Layered decoding architecture 
  • Soft decision decoding

Benefits

  • AR4JA LDPC code is characterized by faster convergence of bit-error rate (BER) with less number of iterations compared to quasi-cyclic codes. Frame-to-frame on-the-fly configuration. 
  • The implemented design supports code rates 1/2 (N=8192, K=4096), 2/3 (N=3072, K=2048) and code rate 3/4(N=4096, K=3072). 
  • A trade-off exists among the design key parameters which are: code rate, decoding latency, power efficiency, throughput, and area. 

What’s Included?

  • Synthesizable Verilog
  • System model (Mat lab)
  • Verilog test bench
  • Comprehensive documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
CCSDS AR4JA LDPC Encoder & Decoder
Vendor
Global IP Core Sales

Provider

Global IP Core Sales
HQ: Germany
Global IP Core Sales was founded in 2021 and provides state-of-the-art IP Cores for the Semiconductor market. The majority of our products are silicon proven and can be seamlessly implemented into FPGA and ASIC technologies. Global IP Core Sales will assist you with your IP Core and integration needs. Our mission is to grow your bottom line.
Contact Global IP Core Sales

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is CCSDS AR4JA LDPC Decoder & Encoder?

CCSDS AR4JA LDPC Decoder & Encoder is a Channel Coding IP core from Global IP Core Sales listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP