100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input
The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm wit…
Overview
The IPrium-100-Gbps-Polar-Encoder-Decoder IP Core implements Successive Cancellation Polar forward error correction algorithm with fully-parallel and unrolled architecture.
Key features
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
- Low implementation loss
- Fully verified and real-time tested on a FPGA based development platform
- Considerations for easy ASIC integration
- Validated on IPrium Evaluation Boards
Applications
- 5G communication systems
- Optical links
- Wireless modems
- Systems with the need of high-throughput FEC Codes
What’s Included?
- VQM/NGC/EDIF netlists for Intel (Altera) Quartus Prime, Xilinx Vivado/ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
- IP Core testbench scripts
- Design examples for Intel (Altera), Xilinx, Lattice, and Microsemi (Actel) evaluation boards
- Free 1 year warranty and support period
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about Channel Coding IP cores
What is 100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input?
100 Gbit/s Polar Encoder and Decoder with soft-decision LLR input is a Channel Coding IP core from IPrium LLC listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.