Vendor: Liancheng Zhixin, Inc. Category: Channel Coding

LDPC Encoder/Decoder for Flash controller

The LDPC IP is a Low-density parity-check code encoder and decoder designed for 3D NAND Flash error correction to address the rel…

UMC 40nm Silicon Proven View all specifications

Overview

The LDPC IP is a Low-density parity-check code encoder and decoder designed for 3D NAND Flash error correction to address the reliability challenges. 1kB, 2kB and 4kB code information lengths are supported.

Key features

  • Strong error correction performance
  • Supporting wide range of data-rates from 0.83 to 0.95
  • No error floor @UBER=10E-15
  • High throughput with low complexity hardware
  • Hard decision and multi-bits soft decoding support
  • Error bits number output when decodable
  • Original frame output when un-decodable
  • Early termination technique

Benefits

  • New software tools:
  • Ultra-low error floor LDPC code construction tool
  • Error floor estimation tool

Applications

  • Flash controller error correction

What’s Included?

  • Source Code for Matlab simulation and matrix information
  • Source Code for fast simulation on Nvidia GPU
  • Verilog HDL Source Code for En/Decoder IP
  • IP Verification Environment
  • FPGA Verification Environment Reference Design
  • IP User Guide
  • IP Test Documantation
  • Integration support including consulting
  • Ultra-low error floor LDPC code construction tool
  • Error floor estimation tool

Silicon Options

Foundry Node Process Maturity
UMC 40nm 40nm 400 nm Silicon Proven

Specifications

Identity

Part Number
LCZX_231
Vendor
Liancheng Zhixin, Inc.

Provider

Liancheng Zhixin, Inc.
HQ: China
Our corporation has been working in the related fields for many years. We are committed to providing customers with efficient, low-cost, easy-to-use IP to jointly promote the development of integrated circuit industry.

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is LDPC Encoder/Decoder for Flash controller?

LDPC Encoder/Decoder for Flash controller is a Channel Coding IP core from Liancheng Zhixin, Inc. listed on Semi IP Hub. It is listed with support for umc Silicon Proven.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP