32-bit RISC-V High Performance Microcontroller Class Processor
VEGA ET1031 is a compact 3-stage in-order 32-bit RISC-V processor core ideal for low power applications.
Overview
VEGA ET1031 is a compact 3-stage in-order 32-bit RISC-V processor core ideal for low power applications. RV32IM RISC-V Instruction Set Architecture based processor is equipped with high performance multiply/divide unit. The processor features separate instruction and data bus to increase performance.
Key features
- RISC-V (RV32IM) ISA
- 3-stage in-order pipeline
- Harvard architecture
- High-performance multiply/divide unit
- Platform Level Interrupt Controller
- Vectored interrupt support
- Configurable AXI4 or AHB interface
- Optional Memory Protection Unit
- Advanced Integrated Debug Controller
- Debug extension allowing Eclipse debugging via a GDB
- openOCD
- JTAG connection
Block Diagram
Applications
- Sensor fusion
- Smart Meter
- System supervisors
- Remote sensors
- Small IoT devices
- Wearable devices
- Motor drives
- Hand held devices
- GPS platforms
- Toys
- Electronic education devices
- PLCs
- Inverters
- Printers & Scanners
- Industrial networking
- Legacy 8/16-bit applications
What’s Included?
- RTL Source Code
- Test Benches
- Synthesis Scripts
- Product Specification
- User Guide
- Integration Guidelines
Video
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about MCU IP cores
What is 32-bit RISC-V High Performance Microcontroller Class Processor?
32-bit RISC-V High Performance Microcontroller Class Processor is a MCU IP core from C-DAC listed on Semi IP Hub.
How should engineers evaluate this MCU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MCU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.