Vendor: Dolphin Semiconductor Category: DAC

24-bit cap-less Audio DAC 120dB SNR low latency

The sDAC-uLP-SW3-LR.01 is a mixed (analog and digital) Virtual Component containing a stereo DAC, and additional functions offeri…

24 Bit TSMC 22nm ULL Pre-Silicon View all specifications

Overview

The sDAC-uLP-SW3-LR.01 is a mixed (analog and digital) Virtual Component containing a stereo DAC, and additional functions offering an ideal digital to analog converter for low dynamic power, low Bill-of-Material and high quality audio applications. It can also combine ultra-low latency capability for ANC applications to demonstrate the best sound quality, while starring the longest playback capability.

Key features

  • I2C and APB control interface
  • Low BoM and capacitor-less headphone driver
  • Pop-Up Noise Reduction system
  • High SNR for high quality playback
  • Programmable ultra low latency capability
  • Ultra-low power mode, ideal for battery powered voice first devices

Block Diagram

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 22nm ULL Pre-Silicon

Specifications

Identity

Part Number
sDAC120-SW3-LR.01_TSMC_22_uLL
Vendor
Dolphin Semiconductor
Type
Silicon IP

Analog

Resolution bits
24 Bit

Provider

Dolphin Semiconductor
HQ: France
Dolphin Semiconductor is a leading provider of semiconductor IP solutions, specializing in mixed signal IP design targeting markets such as Industrial, High-Performance Computing, Consumer Electronics, IoT and Automotive. Dolphin Semiconductor cutting-edge technology IPs in power management, high-quality audio, power metering, and design safety/robustness, allow their customers to accelerate design cycles, foster faster time-to-market and build products that address the challenges of any industry and support a more sustainable world. With a customer-centric approach, Dolphin Semiconductor provides exceptional support for successful project outcomes.

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 24-bit cap-less Audio DAC 120dB SNR low latency?

24-bit cap-less Audio DAC 120dB SNR low latency is a DAC IP core from Dolphin Semiconductor listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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