Vendor:
IP Cores, Inc.
Category:
Public Key
RSA2-AHB Accelerator Core with AHB Interface
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponen…
Overview
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”.
The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, however, typically requiring many seconds of the CPU time for signature verification.
RSA2-AHB implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices.
RSA2-AHB targets compact embedded designs with an ARM AHB bus. Higher performance is available from the RSA5 scalable family of cores.
The core implements the exponentiation operation of the RSA cryptography Q = Pk. The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started. Once the operation is complete, the result Q can be read through the AHB interface.
Options
The core comes in a variety of options:
- Multiplication option (CRT) provides an interface to accelerate the Chinese Remainder Theorem in hardware. Without this option, the default exponentiation-only (E) core still permits the use of the CRT, but requires some CPU support.
- Diffie-Hellmann (-DH) option accelerates an entire Diffie-Hellmann algorithm. Without this option, the DH operations requires some CPU support
- Digital Signature (DSA) option accelerates an entire Digital Signature algorithm. Without this option, the DH operations requires some CPU support
Key features
- Small size: RSA1-E starts from less than 15K ASIC gates size depends on the core configuration)
- Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
- Support for RSA with programmable bit sizes
- ARM TrustZone support (separated access for normal and secure applications)
- Test bench provided
Block Diagram
RSA2-AHB block diagram
Applications
- Secure communications systems
- Digital Rights Management (DRM) for battery powered electronics
- Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31
- Digital Signature Standard (DSS) FIPS-186
- PKCS RSA cryptography per RFC 2347
What’s Included?
- Synthesizable Verilog RTL source code
- Software modules for a complete ECC implementation (optional)
- Verilog testbench (self-checking)
- Software modules test harness
- Vectors for testbench and harness
- Expected results
- User Documentation
Specifications
Identity
Part Number
RSA2-AHB
Vendor
IP Cores, Inc.
Type
Silicon IP
Security
Crypto Algorithm
RSA
Files
Note: some files may require an NDA depending on provider policy.
Provider
IP Cores, Inc.
HQ:
USA
IP Cores, Inc specializes on IP cores for semiconductors, primarily in the security and cryptography area with a sprinkle of DSP. Whether your needs are in 802.16e, P1619, 802.1AE, content protection, or FFT, our cryptographic and DSP cores usually are the smallest, fastest, and lowest-cost choices on the market.
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Frequently asked questions about Public-Key Cryptography IP cores
What is RSA2-AHB Accelerator Core with AHB Interface?
RSA2-AHB Accelerator Core with AHB Interface is a Public Key IP core from IP Cores, Inc. listed on Semi IP Hub.
How should engineers evaluate this Public Key?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Public Key IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.