Vendor: Digital Core Design Category: Hash / MAC

Hash and HMAC Functions Accelerator

The DSHA2-384 - a universal solution that accelerates SHA2-384 hash with HMAC mode.

Overview

The DSHA2-384 - a universal solution that accelerates SHA2-384 hash with HMAC mode.

DSHA2-384 bridge to APB, AHB, AXI bus, it is a universal solution that efficiently accelerates SHA2-384 hash function compliant with FIPS PUB 180-4. It computes message digest in either 256, 224, or 384-bit modes. Allowed input message length is up to 264 – 1 bit. Depending on the core configuration it also natively supports the SHA2-384 HMAC (Keyed-Hash Message Authentication Code), a cryptographic function defined in RFC 2104. This IP is suitable for authenticity and data integrity verification in digital signature protocols and generally in secure communication. It might also be used in accelerating cryptocurrency computations. What is more, it offers a context-swapping feature, which might be used in complex systems with a task’s preemption mechanism. Its other application can be software managed or a custom HMAC scheme. SHA2 is a family of cryptography that secures one-way compression functions based on the Merkle-Damgard structure, the 256 version sequentially processes 512-bit input blocks during 64 rounds. From arbitrary length input message (maximum 264 – 1 bits) it produces fixed 256 or 224-bit length digest in a way, that it is practically infeasible to invert it (get an original message from its digest). Such a property is called a one-way function. The cryptographic security of SHA2-384 is assumed at 128-bit level (112-bit in the case of SHA2-224) which makes it appropriate for use in security applications. Some of these applications need to prove knowledge or possession of some secret data while computing message digest. For such authentication purposes, the HMAC function has been designed. It combines both secret key and cryptography secure hash function (like SHA2-256).

Key features

  • FIPS PUB 180-4 compliant SHA2-256 function
  • RFC 2104 compliant HMAC mode native support
  • SHA2 224 and 256 bit modes support
  • Secure storage for precomputed HMAC keys
  • Hash/HMAC context swapping
  • Internal, automatic padding module
  • Binary message resolution support
  • Flexible data read/write modes
  • Software support:
    • Software driver with OpenSSL/MbedTLS interface ready
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

Block Diagram

Applications

  • Digital signature
  • Data integrity
  • Key derivation
  • TLS/SSH/PGP IPsec communication

What’s Included?

  • HDL Source Code
  • Testbench environment
    • Automatic Simulation macros
    • Tests with reference responses
  • Synthesis scripts
  • Technical documentation
  • 12 months of technical support

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
DSHA2-384
Vendor
Digital Core Design

Provider

Digital Core Design
HQ: Poland
Founded in 1999, Digital Core Design is a global leader in IP core development, specializing in microprocessor, microcontroller, and communication solutions. With a portfolio of over 100 IP cores, DCD continues to drive innovation in embedded systems, providing cutting-edge solutions for automotive, industrial, IoT, and security applications.

Learn more about Hash / MAC IP core

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Frequently asked questions about Hash / MAC IP cores

What is Hash and HMAC Functions Accelerator?

Hash and HMAC Functions Accelerator is a Hash / MAC IP core from Digital Core Design listed on Semi IP Hub.

How should engineers evaluate this Hash / MAC?

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