Vendor: Small World Communications Category: Channel Coding

Very High Speed 8 State MAP Decoder

This is a very high speed 8 state maximum a posteriori (MAP) soft-in-soft-out (SISO) triple interleaved error control decoder wit…

Contact Provider Request Datasheet

Overview

This is a very high speed 8 state maximum a posteriori (MAP) soft-in-soft-out (SISO) triple interleaved error control decoder with log-likelihood-ratio outputs for both the data and parity bits.

Key features

  • 8 state soft-in-soft-out (SISO) maximum a posteriori (MAP) triple interleaved error control decoder and systematic recursive convolutional encoder
  • Up to 120 Mbit/s decoding speed for all states
  • Rate 1/2, 1/3, or 1/4 with optional punctured inputs
  • 6-bit received data, 8-bit soft-in and soft-out data for information and parity bits for all rates
  • 8-bit branch metric inputs for rate 1/2
  • Optional code polynomials
  • Optional block decoding with or without tail
  • Optional max-log-MAP or log-MAP algorithm with 9 or 17 programmable SNR's
  • Continuous sliding block algorithm with sliding block lengths of 32 or 64
  • Low decoding delay (398 or 782 CLK cycles)
  • No external RAM required
  • Asynchronous logic free design
  • Ideal for iterative decoding of 3GPP turbo codes
  • Low power mode and synchronous reset
  • Available as EDIF/VHDL cores or BIT/MCS files for download into Xilinx Virtex, Virtex-E, Virtex-II, Spartan-II, and Spartan-IIE FPGAs. Actel, Altera and Lattice FPGA cores available on request.
  • Support for ASIC cores is also available
  • 3GPP is a trademark of ETSI

What’s Included?

  • EDIF core
  • VHDL simuluation core
  • Test vector generation software

Specifications

Identity

Part Number
MAP03T
Vendor
Small World Communications
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Small World Communications
HQ: Australia
Small World Communications was started in January 1997 and is located in Adelaide, Australia. We specialise in error control decoder products for programmable gate arrays.
Contact Small World Communications

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is Very High Speed 8 State MAP Decoder?

Very High Speed 8 State MAP Decoder is a Channel Coding IP core from Small World Communications listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP