Vendor: StarIC Inc Category: Power Management Unit

Cascoded GaN high voltage driver

STAR2040 is a CMOS cascode driver circuit designed for use with high-current GaN (or SiC) power FET devices.

Overview

STAR2040 is a CMOS cascode driver circuit designed for use with high-current GaN (or SiC) power FET devices. It can be operated with 20 A of current, with a typical on-resistance of <15 milliohms. In a typical usage scenario, the driver can achieve a switching frequency as high as 2 MHz. This permits the use of small external passive components in switching converter applications, and hence a low BOM. The driver is implemented in a standard 5-V CMOS process, without the need for any special high-voltage devices. It requires a single 5-V power supply (VDD).

The driver state is controlled by a differential pair (INP and INM) of 5-V CMOS logic signals; this signalling scheme provides rejection of common-mode noise. Due to the on-chip pre-driver, the drive-current requirement for the INP and INM pins is small. STAR2040 incorporates a variety of monitoring and safety features, such as: (1) an integrated protection diode for the drain node; (2) an integrated analog temperature sensor; (3) a tunable rise/fall-time control circuit; and (4) monitoring capability for the drain, gate, and source nodes. Because of its high current capability, low on-resistance, and high switching frequency, STAR2040 is ideally suited for high-current, high-voltage switching converter applications that require the use of GaN (or SiC) devices. This potentially includes applications such as electric vehicles, high-current appliances, and power supplies for laptop computers.

Key features

  • Current handling: up to 20 A
  • Typical on-resistance: <15 milliohms (@ 20 A)
  • 2-MHz switching capability
    • Permits use of smaller external components
  • Implemented using commodity 5-V CMOS process
    • No high-voltage process required
  • Single 5-V power supply required
    • Current draw: 1.2 A peak, 24 mA average (for 2-MHz switching)
  • 5-V CMOS logic levels used for input control signals
    • Differential signalling used (for better common-mode rejection in noisy environments)
    • Typical input current < 1.5 mA peak (for 4-ns rise/fall time)
    • Output rise/fall time is insensitive to input rise/fall time
  • Additional features: – Built-in protection diode keeps drain node safe – Built-in analog temperature sensor – Rise/fall-time control at gate (set by optional external resistor) – Analog monitoring of drain, gate, source nodes
  • Die size: 4.05 mm x 4.05 mm – Drain connections designed for vertical packaging with GaN device – Source connections can be made with TSVs, for completely vertical current flow

Block Diagram

Applications

  • High-current, high-voltage dc-dc converters
    • Electric vehicles
  • High-current ac-dc converters
    • High-current appliances
    • Power supplies for laptop computers

What’s Included?

  • .gds layout database
  • .lib liberty timing models
  • .lef layout exchange format files
  • Extensive documentation
  • Customer support/integration package
  • Design usage training
  • Schematics available
  • Secured online portal

Specifications

Identity

Part Number
STAR2040
Vendor
StarIC Inc
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

StarIC Inc
HQ: Canada
StarIC enables innovative and high-performance ASIC and system solutions and IP. Based in Toronto, Canada our team is led by industry veterans and highly experienced experts in the field of mixed-signal design. Many have worked together as a team through prior companies for a number of years. In addition to extensive experience managing and running semiconductor companies, all of StarIC’s leadership have strong engineering backgrounds. At StarIC world-class engineering is at the core of our identity.

Learn more about Power Management Unit IP core

A versatile Control Network of power domains in a low power SoC

Developing and verifying a control network in a low-power SoC is a challenging task, especially managing the different states of regulators and modes of power domains. This article first describes state-of-the-art approaches to addressing this issue, and then delves into the solution promoted by Dolphin Integration to go further, thanks to the easy and secure Maestro� solution to manage SoC power mode transitions.

An ESD efficient, Generic Low Power Wake up methodology in an SOC

As the semiconductor industry is moving towards lower technology nodes, more and more complexity is being introduced in the design to beat the competition and provide most innovative solution to cater the needs. One of the biggest challenges that the designer faces is in terms of the keeping the power budgets of the chip within the specification and even innovate to reduce the current numbers. Depending on the application requirements, the designers have to tune up the power profile of the SoC. There are various ways to do so like dynamically changing frequency and voltage of operation, considering system level contributions to power consumption, using various modes of operation etc. In most of the cases, SoC has to support various power modes like Run mode, Sleep mode, Halt mode etc. Different power numbers are defined for each mode. Run modes can further be divided in various sub modes depending on application.

D32PRO, scalable & royalty free 32-bit CPU

D32PRO is one of the newest 32-bit CPUs available on the market. It’s been designed by Digital Core Design, IP Core provider and SoC design house from Poland, responsible e.g. for the world’s fastest or world’s smallest 8051 CPU. DCD launched more than 70 different architectures since 1999, which have been implemented in more than 300 000 000 electronic devices, that’s why one can be sure that quite considerable experience stands behind the D32PRO.

Semiconductor IP FAQ

What is Cascoded GaN high voltage driver?

Cascoded GaN high voltage driver is a Power Management Unit IP core from StarIC Inc listed on Semi IP Hub.

How should engineers evaluate this Power Management Unit?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power Management Unit IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP