Vendor: IP-Maker Category: Channel Coding

BCH Encoder/Decoder IP Core

Nand Flash write cycles are limited.

Contact Provider Request Datasheet

Overview

Nand Flash write cycles are limited. An ECC detects and corrects failed operations, increasing the lifetime of the Nand Flash memory. For Nand Flash-based data storage, using an ECC is mandatory to ensure data validity. The powerful IPM-BCH is based on the BCH algorithm.

The BCH Encoder/Decoder is full-featured with multiple parameters to fit your own needs in FPGA and SoC designs. In fact IPM-BCH Encoder/Decoder is fully configurable, allowing to it reach the best latency or the smallest footprint.

Key features

  • IPM-BCH for NandFlash Storage
    • Up to 84 error-bits/block
    • Configurable block size
  • IPM-BCH for short code
    • Option to be full asynchronous
    • Option to be in 3 clock cycles
  • Fully Configurable
    • Latency
    • Datapath
    • Error number
    • Packet size

Block Diagram

IPM BCH block diagram

Benefits

  • Full hardware implementation for
  • maximum performance, encoding,
  • error detection and correction
  • Balanced performance/gatecount
  • All Galois fields covered
  • Validated IP reduces Time-ToMarket

What’s Included?

  • Verilog RTL source code.
  • Synthesis scripts for Xilinx, Altera and Design Compiler.
  • Technical documentation.
  • Simulation testbench, with error injection.
  • One year of maintenance and technical support.
  • Supported simulators
    • MTI Modelsim.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
IPM BCH
Vendor
IP-Maker

Provider

IP-Maker
HQ: France
IP-Maker is a young and dynamic team of senior electronic engineers who will help your company leverage on the latest technological improvement and development in the area of memories (NAND Flash). Our team of highly-qualified engineers and project managers works in a very client-orientated manner focusing on fit-for-purpose solutions and controlled planning.
Contact IP-Maker

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is BCH Encoder/Decoder IP Core?

BCH Encoder/Decoder IP Core is a Channel Coding IP core from IP-Maker listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP