8/10/12-bit Extended JPEG Decoder
The JPEG-D-X core is a standalone and high-performance JPEG decoder for still image and video compression applications.
Overview
The JPEG-D-X core is a standalone and high-performance JPEG decoder for still image and video compression applications. Compliance¹ with the Baseline and the Extended Sequential DCT modes of the ISO/IEC 10918-1 JPEG standard makes this core suitable for interoperable systems and devices. The JPEG-E-X is available for ASIC or AMD-Xilinx, Efinix, Intel, Lattice and Microchip FPGA and SoC based designs.
In addition to decoding standard compliant Baseline and Extended JPEG streams, the core is also capable of decompressing the video payload of many (de facto) standard motion JPEG container formats.
The core is designed with simple, fully controllable and FIFO like, streaming input and output interfaces. Being carefully designed and rigorously verified, the JPEG-D-X is a reliable and easy-to-use and integrate IP.
Key features
- Complete, Compliant and Standalone Operation
- ISO/IEC 10918-1 compliant 8-bit Baseline and 12-bit Extended JPEG decoder
- Up to 64K x 64K image resolution
- Up to four 8-bit or 16-bit stream programmable Quantization Tables
- Up to four stream programmable Huffman Tables (two DC, two AC)
- Stream programmable Restart Markers
- Single- and multi-scan support
- All three compressed data formats supported
- Interchange format
- Abbreviated format for compressed image data
- Abbreviated format for table-specification data
- Motion JPEG payload decoding
- CPU-less, complete and standalone operation
- Limitations with Respect to the ISO/IEC 10918-1 JPEG Standard
- Up to 4 image components
- Sampling factors 1, 2 and 4
- Up to 4 Huffman Tables
- The DNL marker is not supported
- Decoding of corrupted JPEG streams is not supported
- Ease of Integration
- Automatic self-programming by JPEG markers parsing
- JPEG marker errors catching features
- Simple, microcontroller like, programming interface
- High-speed, flow controllable, streaming I/O data interfaces
- Simple and FIFO like
- Avalon-ST compliant (ready latency 0)
- AXI4-Stream compliant
- Trouble-Free Technology Map and Implementation
- Fully portable, self-contained RTL source code
- Strictly positive edge triggered design
- D-type only Flip-Flops
- Fully synchronous operation
- No special timing constraints required
- No false paths
- No multi-cycle paths
Block Diagram
What’s Included?
- Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
- Release Notes, Design Specification and Integration Manual documents
- Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
- Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
- Self-checking testbench environment sources, including sample BAM generated test cases
- Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about Image Conversion IP core
Nextreme Structured ASICs: An alternative for designing cost-optimized ARM926EJ processor-based embedded systems
Video Messaging for ARM7-based Cellular Chipsets.
Configurable Processors for Video Processing SOCs
Generating High Speed CSI2 Video by an FPGA
Viewpoint: Opportunity to win on different design fronts
Frequently asked questions about image conversion IP cores
What is 8/10/12-bit Extended JPEG Decoder?
8/10/12-bit Extended JPEG Decoder is a Image Conversion IP core from Alma Technologies listed on Semi IP Hub.
How should engineers evaluate this Image Conversion?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Image Conversion IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.