ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash co…
Overview
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash controller IP. MDLL sets the delay time for the control signal of PHY to access to the data in flash during the suitable period. Please refer to the following diagram for an overview of ONFI PHY
Key features
- Support ONFi 4.1 IO Electrical Specification
- Support Legacy up to 50MHz
- Support NV-DDR2 up to 533Mbps
- Support NV-DDR3 up to 1200Mbps
- Per DQ (per bit) delay line for controlling skew
- SDLL is included for DQS/DQ phase tuning by DLY setting
- On die De-coupling capacitor (>1nF per channel) for Power Integrity to save PKG capacitor
- Operation temperature: -40 to 125 °C
- Flip-Chip
- Supported metal scheme:
- 1P9M_2Xa1Xd3Xe2Z
- 1P10M_2Xa1Xd4Xe2Z
Block Diagram
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 12nm | FFC | In Production |
Specifications
Identity
Provider
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Frequently asked questions about Single-Protocol PHY IP
What is ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)?
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC) is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.