Overview
The Synopsys Duet Packages of Embedded Memories and Logic Libraries, part of Synopsys Foundation IP portfolio, offer an integrated portfolio of standard cell libraries, memory compilers and memory test and repair capability. The optimized combinations of high-performance and high-density SRAMs, register files, ROMs, standard cells, and Power Optimization Kits (POKs) provide all the elements needed to implement a complete system-on-chip (SoC). Options for overdrive/low voltage, process, voltage, temperature corners (PVTs), high-density SRAMs and multi-channel logic standard cells are also available, enabling designers to achieve the highest quality of results for their SoC in their specific application.
An additional High Performance Core (HPC) Design Kit provides a suite of high-speed and high-density memory instances and logic cells specifically designed to enable SoC designers to optimize their CPU, GPU and DSP cores for maximum speed, smallest area, lowest power or an optimum balance of the three.
Learn more about Standard Cell Libraries IP core
Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use.
Adaptability is essential for digital twin systems due to constantly evolving environments – Learn how eFPGA hardware enables robust and adaptable systems
The free lunch offered for decades by Moore’s law is now over and scaling down to the next technology node no longer offers the required energy efficiency gains. Design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the demands of the new IoT markets.
In this article, we are going to understand how we can solve the gross simulation failure by understanding and editing the SPF skeleton at ATPG stage.
Eric Esteve
