Provider
Vervesemi Microelectronics PVT LTD
HQ:
INDIA
Vervesemi is a fabless semiconductor company incorporated in 2017 and developing high performance ASICs for sensors and wireless, exploiting the expertise of state-of-art data converters and differentiated Analog IP. We are team of analog and RF experts developing Analog solution for semiconductor world. It is a company with high innovation quotient formed by management & technologist having vast experience in semiconductor business.
Vervesemi commits to develop innovative products and analog IP solution for various semiconductor applications market such as Energy, 5G market, ADAS, Medical, consumer, and Smart Power. Vervesemi focus is on breakthrough innovations in high end analog and RF market through state of art designs and significantly differentiated PPA. Vervesemi is developing ASIC for sensor application, energy metering, IC for seismic business. Vervesemi has silicon qualified high speed converters suitable for 5G, Microcontroller, Medical and networking application. The IPs are in various technology flavour e.g. TSMC 28nm, UMC 28nm, UMC 40nm, TSMC 180nm, SMIC 180nm, Samsung 8nm.
In past, Vervesemi accumulates 2 decade of semiconductors design experience in state-of-art data converters for various market segments, producing 50+ IPs on 30 products per year. In that process, the team has achieved vast silicon maturity experience on 20+ technology nodes with overall 300+ matured products having these IPs. The past expertise is in technology node from 0.25u to 28nm including high voltage, SOI and Space technology. It involved expertise in maturing IPs in automotive, microcontroller, consumer, MEMS, Space applications.
Learn more about ADC IP core
This paper introduces a novel closed-loop testing methodology for efficient linearity testing of high-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). Existing test strategies, including histogram-based approaches, sine wave testing, and model-driven reconstruction, often rely on dense data acquisition followed by offline post-processing, which increases overall test time and complexity.
Analog to digital converters have three key input ports along with data output ports as per digital resolution requirements. These inputs ports are Analog Signal, Reference and Clock. If we compare across most of the converter architectures then clock frequency is directly related to output data rate and latency of the data conversion.
The growing availability of digital ICs like microcontrollers, microprocessors, and field-programmable gate arrays (FPGAs) allows developers to use complex digital processing techniques rather than analog signal conditioning. For this reason, analog-to-digital converters (ADCs) have become a widely-used component in mixed-signal circuits.
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
Power-sensitive applications such as Internet-of-Things (IoT) require a comprehensive power savings strategy within the system-on-chip (SoC). Techniques relying solely on the use of traditional power down modes and low supply voltage may not be enough to achieve the required power targets. The analog block is often assumed to be too sensitive and not compatible with aggressive power management techniques.
When continuously running a high speed ADC, it can be a challenge to deal with the firehose of raw data available at the output. To use City Semiconductor’s 2.5 GS/s 12-bit ADC, for example, 30 gigabits per second of data have to be accepted.