Unleash Maximum Throughput

Hyperscale data centers need access to ultra-efficient interfaces to support multi-trillion parameter AI compute models. Synopsys’ UALink IP solution offers maximum throughput per lane at 200 Gbps, providing the performance needed to scale-up to 1,024 AI accelerator links. Consisting of controller, PHY, and verification IP, the complete UALink IP solution is engineered for data-intensive AI workloads offering low latency, high bandwidth, and advanced memory sharing capabilities. Built on decades of design experience in high-speed PCIe and Ethernet IP, Synopsys’ UALink IP reduces integration risk and speeds time to market for AI and HPC chip designers unleashing next-gen AI infrastructures. 

Key Benefits

Features

  • Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
  • Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
  • Enables maximum throughput with up to 200Gbps per lane
  • Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU
  • Supports high density, high radix networking infrastructure for AI workloads
  • Enables full hardware security needs for UALink specifications
Synopsys UALink IP Solution

News and Blogs

Related Products and Solutions

Synopsys provides the industry’s broadest IP portfolio for HPC and AI, enabling designers with best-in-class IP interfaces so designers can speed time to market and achieve first pass silicon success.

Resources

Synopsys 224G IP Solution Shows Widest Multi-Vendor Interop at ECOC 2024
See our 224G Ethernet PHY IP demonstrate excellent performance through a variety of channels and vendors, including VSR and LR, including ISI, mated MCB/HCB, and DAC/ACC. Our 224G PHY IP is an integral part of the complete 1.6T Ethernet IP solution.
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        Synopsys 224G IP Solution Shows Widest Multi-Vendor Interop at ECOC 2024

        Synopsys 800G MAC, PCS and PHY IP Interop with Switches and Optical Links at ECOC '24
        See our 800G Ethernet subsystem with 8 lanes of 112G, MAC and PCS in Frankfurt, our demonstrate 800Gbps Ethernet traffic via optical links and Juniper switches, achieving zero BER over a 3m DAC and zero post FEC errors.
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              Synopsys 800G MAC, PCS and PHY IP Interop with Switches and Optical Links at ECOC 2024

              World's First PCIe 7.0 Controller IP Demonstration at PCI-SIG DevCon 2024
              See the world’s first PCIe 7.0 RC to EP link-up to L0 using EQ bypass mode, with FLIT transfer and throughput measurement using Synopsys PCIe 7.0 Controller IP. Synopsys offers the world's first complete solution for PCIe 7.0 IP.
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                    World's First PCIe 7.0 Controller IP Demonstration at PCI-SIG DevCon 2024

                    PCIe 7.x, PCIe 6.x and 224G Over Optics at OFC 2024
                    Watch Synopsys PCIe 7.x and PCIe 6.x equalizing a full E-O-E Link using OpenLight's PIC and Synopsys 224G TX over optics performance with OpenLight’s 200G per Lambda PIC, enabling Linear/direct drive without retimers.
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                          PCIe 7.x, PCIe 6.x and 224G Over Optics at OFC 2024