SPDIF IP

Overview

The SmartDV SPDIF IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SOC or FPGA development. The SPDIF IIP can be implemented in any technology. The SPDIF IIP core supports the SPDIF 2.2A standard. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon PLB, Tilelink or custom buses.

Key Features

Full SPDIF functionality as per specs.
Supports Variable sampling/Driving rates (32 kHz/44.1 kHz/48 kHz/88.2 kHz/96 kHz/176.4 kHz/192 kHz)
Supports 20/24 bit samples
Synchronization holds in the under-run condition, clock recovery from the SPDIF data stream.
Sample rate detection from the received data stream
Supports both transmit and receive function.
Options Host control interface (DMA engine).
Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

The SPDIF IP interface is available in Source and netlist products.
The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases.
Lint, CDC, Synthesis and Simulation Scripts with waiver files.
IP-XACT RDL generated address map.
Firmware code and Linux driver package.
Documentation contains User s Guide and Release notes.

Technical Specifications

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