PCIe Gen1 PHY

Overview

The PCIe1 PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into computer applications. The PCIe1 PHY pcie1_pipe_1xN includes all the necessary logical, geometric, and physical design files to implement complete PCI Express 1.1 physical layer capability for 2.5-Gbps operation, connecting a host or device controller to a PCI Express system.

Key Features

? 2.5-Gbps data transmission rate
? Supports 16-bit interface at 250-MHz operation
? Supports 32-bit interface at 125-MHz operation
? Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
? Programmable Rx equalization
? Supports collapsing of power supplies
? Supports x1/x2/x4 configurations
? Supports low power mode
? Integrated regulator to support both 3.3-V or 2.5-V I/O power supply
? Excellent performance margin and receiver sensitivity
? Robust PHY architecture that tolerates wide process, voltage, and temperature variations
? Low-jitter PLL technology with excellent supply isolation
? IEEE 1149.6 (JTAG) boundary scan
? Built-in Self-Test (BIST) features for production, at-speed testing on any digital tester
? Supports 2.5-Gbps PCIe Gen 1.1 test mode
? Advanced, built-in diagnostics including on-chip sampling scope for easy debug
? Visibility and controllability of hard macro functions through programmable registers in the design
? Overrides on all ASIC side inputs for easy debug
? Access register space through simple 16-bit parallel interface
? Access register space through JTAG port

Deliverables

We offer high-speed interface IPs designed for 28~90nm fabrication processes in various foundries. We can also customize porting IPs for customers requiring 90~180nm fabrications and support more advanced processes as needed.

Technical Specifications

Foundry, Node

TSMC,40,65; GF,40

Maturity

Silicon Proven

Availability

Immediate

GLOBALFOUNDRIES

Silicon Proven: 40nm LP

TSMC