low-pin-count APB component
Overview
CoreLPC is a low-pin-count (LPC) advanced peripheral bus (APB) component which accepts LPC host-side system interface commands to the APB-side software driver interface. Logic is included to assist in the software driver's implementation of the keyboard controller style (KCS) protocol. Serial interrupt request (SERIRQ) logic can also be included by asserting the SERIRQ_EN parameter. CoreLPC is APB3-compliant, enabling easy integration with systems built around the ARM Cortex-M1, Core8051s, or CoreABC microcontrollers.
Key Features
- Support for LPC peripheral interface (as required by the LPC specification revision 1.1)
- I/O read/write LPC cycle types
- Support for the KCS protocol over the LPC interface (as described in the IPMI specification v2.0)
- Raised internal interrupt request (IRQ) on receipt of data from host controller
- Serialized IRQs communication to the host controller
- LPC controller enabling/disabling by software
- Configurable base LPC address for each LPC function on which the controller responds to LPC transactions
- APB3-compliant
Technical Specifications
Related IPs
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- APB Fundamental Peripheral IP, I2C controller, Soft IP
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- APB Fundamental Peripheral IP, IO controller, Soft IP