32/64-bit NeuroMatrix(r) RISC Core (NMRC)

Key Features

• original RC Module RISC architecture
• 32- and(or) 64-bit data paths
• advanced Harvard architecture
• extended architecture for 32- or 64-bit co-processor
• 16-Gbyte address pace
• dual-channel DMA controller
• two address generators support up to two memory accesses per cycle
• five-stage pipeline
• 10 bypass paths to minimize the effect of pipeline latency on dependent operations
• 32-bit VLIW instruction
• up to three operations per instruction
• load-store architecture
• delayed branches to reduce pipeline disruption
• easy to add new instructions
• easy to add 32x32 bit array multiplier
• strong SDK and Evaluation Boards

Benefits

• 50MHz clock rate
• 50MIPS
• 150MOPS (32-bit data)
• 35K eq.gates
• 2x5 sq.mm die size at 0.5um CMOS technology

Deliverables

• NMRC DESIGN DATABASE
• Synthesizable RTL Verilog source code of NMRC core
• Install script
• Synopsys DC synthesizer scripts
• NMRC SOFTWARE DEVELOPMENT TOOLS
• PROFESSIONAL NMRC SDK
• NMRC SDK. Programmer's guide
• NMRC Assembly Language Overview
• NMRC SDK. Load and exchange library
• Application notes with source code examples
• NMRC TEST SUITE
• Verilog Behavioral description which describes test-bench environment and generates the test stimulus to external NMRC interfaces (main NMRC interfaces, interrupts etc.)
• Test bench for running a compiled/assembled test program from the linker output file format
• Exhaustive test program/vectors - runs all instructions and all modes
• NMRC DOCUMENTATION
• A flyer, summarizing the key features of the NMRC core
• Technical data sheet, summarizing interfaces, features and performance
• Design documentation including block diagrams
• Functional specification for all external interfaces
• Documentation of the synthesis scripts.
• Documentation of debug/test/emulation features

Technical Specifications