With increasing demand in next-generation data centers and high-performance computing and networking, wireline transceivers are required to operate at 112Gb/s to provide high bandwidth [1]–[3], meanwhile it is necessary to handle >40dB insertion loss to support legacy channels and large package designs [4]. Low-power design is also critical for the integration of multiple transceivers [5]. To advance state-of-the-art design, this work presents an ADC/DAC-DSP based PAM-4 transceiver capable of equalizing >50dB lossy channels and achieving 112.5Gb/s per channel in a 5nm FinFET process with a power efficiency of 4.5pJ/b.