Wrapper IP building blocks for ES1 IP

Key Features

  • GMII 2 RGMII/SGMII adapter: PHYs and SFPs; built-in MDIO / I2C controller for -PHY
  • Memory protection for high integrity/availability systems: SEC/DED protection of TTE End System Core Memories; built-in self-test of memories; memory scrubbing
  • TTE end system core streaming adapter: Allows interfacing TTE-ES core from user application via packet interface (AXI-S)
  • TTE end system core DMA engine: Support for high latency buses like PCIe while reaching line (1Gbps) throughputs. Customization for any PCIe HARD IP is possible; variant of DMA for SoC use (AMBA interfacing)

Benefits

  • Capacity: 2 channels (100/1000 Mbps selectable)

Applications

  • Allows efficient integration of ES1 IP to various systems

Technical Specifications

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Semiconductor IP