OCP Synthesizable Transactor provides a smart way to verify the OCP component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's OCP Synthesizable Transactor is fully compliant with standard OCP Specification 3.1 and provides the following features
OCP Synthesizable Transactor
Overview
Key Features
- Compliant with OCP 3.1 specification
- Supports OCP Master, OCP Slave
- Supports all OCP protocol transfer & command types
- Supports all OCP protocol signal widths including address and data
- Supports all OCP protocol burst models, burst lengths and response types
- Supports SRMD and MRMD bursts
- Ability to pipeline transfers and non-blocking flow control support
- Supports concurrency and out-of-order processing of transfers
- Multi-threading and tagging support
- Supports Request interleaving
- Master/Slave Connect-Disconnect feature support
- Supports 2-Dimensional block burst address sequences
- Compliance to phase-ordering rules
- Complete support for full range of OCP configurations
- Supports asynchronous/synchronous reset and EnableClk mechanism. On the fly reset control
- Supports threadBusy behavior
- Supports all sideband signals
- Supports coherence extensions
- Slave supports fine grain control of response per address or per transfer
- Supports programmable timeout insertion
- Supports on-the-fly protocol and data checking
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
Block Diagram
Deliverables
- Synthesizable transactors
- Complete regression suite containing all the OCP testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all class, task and functions used in verification env
- Documentation contains User's Guide and Release notes