IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI CSI-2 IP > MIPI CSI-2 Receiver IP

MIPI CSI-2 Receiver IP

Overview

MIPI CSI-2 Receiver interface provides full support for the two-wire MIPI CSI2 serial interface, compatible with MIPI CSI-2 Specification version 2.1. It is typically residing in an image application processor and provides communication to MIPI CSI-2 transmitter in a camera module over the serial PHY link. MIPI CSI-2 Receiver IIP is fully configurable and proven in FPGA environment. The host interface of the MIPI CSI-2 Receiver IP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

Key Features

  • Compliant with MIPI CSI-2 Specification v1.0, v1.1, v1.3, v2.0,v2.1
  • Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
  • Compliant with C - PHY Specification v0.7,v1.2
  • Full MIPI CSI-2 RX functionality where either D - PHY / C - PHY can be used
  • Supports Multi lane merging and also lanes can be configured up to 4 lanes for C - PHY and 8 lanes for D Ã?Ã?ô PHY
  • Supports Data rate up to 4.5 Gbps per data lane of D Ã?Ã?ô PHY. 36 Gbps in 8 Lanes
  • Supports Data rate up to 3 Gsps per trio using C Ã?Ã?ô PHY. 17 Gbps in 3 Trios
  • Supports up to 4 Virtual channels
  • Supports continuous and non-continuous clock modes
  • Supports PPI Interface to connect to C - PHY / D - PHY
  • Supports short and long packets.
  • Supports Frame and Line Synchronization Packets (Short Packets)
  • Supports Data Descrambling in Lanes
  • Supports Deskew mechanism for Lane synchronization.
  • Supports High Speed and Escape Mode (LPDT and ULPS) reception
  • Supports the following interleaving methods
    • -> Data type
    • -> Virtual channel
  • Supports 1-bit Error Correction and 2-bit Error Detection using ECC (6 bit) for Packet Header.
  • Supports Error Detection techniques for active data using Checksum (16 bit).
  • Supports 16 interleaved Virtual channel in D-PHY and 32 in C-PHY
  • Support all Protocol Decoding Level errors
  • Supports the compression for RAW data types
  • Supports Error Detection techniques for active data using Checksum (16 bit)
  • Supports Image applications with varying Pixel format
    • -> RAW Data Type - RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, RAW20, RAW24
    • -> RGB Data Type - RGB444, RGB555, RGB565, RGB888, RGB 666
    • -> YUV Data Type - YUV422-8bit, YUV422-10bit, YUV420-8bit, YUV420-10bit, Legacy YUV420-8bit
    • -> User defined data type - 8 data types
    • -> Generic 8 bit long packet (Null, Blanking, Embedded data)
  • Supports Pixel Level /interface to ISP with HSYNC, VSYNC, DATA and DATA VALID
  • Programmable synchronization and interrupt (error and information) events
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

  • The MIPI CSI-2 Receiver interface is available in Source and netlist products
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User s Guide and Release notes

Technical Specifications

Maturity
Getting used at customer site
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