Dual Port SRAM Compiler IP, UMC 0.11um LL process
Overview
UMC 0.11um low leakage Logic process synchronous high density Dual Port SRAM memory compiler.
Technical Specifications
Foundry, Node
UMC 110nm LL
UMC
Pre-Silicon:
110nm
Related IPs
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Rail - compiler range up to 288 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Single Port SRAM compiler - Memory optimized for ultra high density and low power - 3ML- compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k
- Single Port SRAM compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 640 kbits
- Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k