Digital Signal Processor IP
Overview
VeriSilicon's programmable ZSP Digital Signal Processor IP is a series of processor cores optimized for signal processing computation and data streaming, for building cost effective embedded solutions for a wide range of applications, including audio, voice, imaging, vision, wireless connectivity, and power line communications fields. VeriSilicon's ZSP Series IP is optimized for different applications and can be used to match different PPA and system requirements.
Key Features
- • High performance vector signal processing
- and efficient control code processing
- • 128 8-bit macs, 64 16-bit macs, or 32 32-bit macs per cycle
- • Flexible vector permute operations
- • Maskable vector lanes
- • 8/16/32/64 bit data types
- • 1K-bit data bandwidth
- • TCM and Cache memories
- • Up to 32 scaler/gather per cycle
- • ZTurbo interface for custom instructions
- and accelerators
- • Optional vector & scalar FPUs
- • Low power modes of operation
- • Compatible, Scalable Roadmap
Technical Specifications
Foundry, Node
All
Maturity
Silicon Integration
Availability
now
Related IPs
- 16-bit digital signal processor soft core
- 16-bit digital signal processor soft core
- 24-bit digital signal processor soft core.
- Digital Signal Processor (DSP) for image processing
- Digital Signal Processor Software compatible with the TI 320C50, 320C51, 320C52 and 320C53
- Ultra low power C-programmable Baseband Signal Processor core